• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    1. DEVICE FOR PHASING OF NUMERICAL SEQUENCES, containing the first comparison unit, a pulse generator, the first memory block, a counter, a phase shifters block, differing in that, in order to increase the reliability of the transfer, a second memory block, an OR element, a second counter the second comparison unit, the decision unit, the phase discriminator, the output of the first comparison unit is connected to the first input of the first memory block, the output of which is connected to the first input of the second memory block, and the pulse generator code is connected to the second The first and second memory blocks, the spring code of the second memory block are connected to the first input of the first counter, the code of which is connected to the first inputs of the OR element and the second counter, the output of the OR element is connected to the control input of the phase shifter unit, the first and second outputs of the second counter connected respectively to the second input of the first counter and to the first input of the decision block, the first output of which is connected to the first input of the second comparison unit, the output of which is connected to the second input of the second counter, the second the progress of solving its block is connected to the second input of the OR element, the output of the phase discriminator is connected to the second input of the decision block, the inputs of the first comparison block, the phase discriminator i and the information inputs of the phase blocks. The rotators are the information inputs of the device, the input of the second comparison unit is the control input of the device, the outputs of the phase switch block are the information outputs of the device, the first output of the PEMBJw, the decider of the device is the control output of the device. 2. The device according to claim 1, 1, that the decisive Ol block contains flip-flops, the output of the first flip-flop is connected to the first input of the second flip-flop, the second input of which is connected to its first output, the first inputs of the first and third flip-flops are combined and are the first input of the decision block; the second inputs of the first and third flip-flops are combined and are the second input of the decision block; the second output of the second flip-flop is the first output of the decision block, the output of the third flip-flop is the second output of the decision block.
    公开号:SU1181567A3
    申请号:SU823437215
    申请日:1982-05-05
    公开日:1985-09-23
    发明作者:Анри Аб Дер Альден Шарль；Анри Беренгиер Пьер
    申请人:Сосьете Аноним Де Телекоммюникасьон (Фирма)；
    IPC主号:
    专利说明:

    eleven
    The invention relates to the digital transmission of information and, in particular, to the phasing of numerical sequences to provide the switching order, with HasBaHiibie rows containing signals of identical data and a synchronization signal of the same frequency.
    The purpose of the invention is to increase the reliability of transmission,
    FIG. 1 shows the proposed device J in FIG. 2; the decisive block; FIGS. 3 and 4 are the time-isch diagrams of the device operation.
    The device contains the first comparison unit 1, the first memory block 2, the pulse generator 3, the second memory block 4, the second comparison block 5, the first counter 6j, the second counter 7, the decisive block 8, the element OR 9, the correlator 10, consisting from blocks 1–4, phase discriminator 11, logical node 12, consisting of blocks 5--9, and block 13 of phase shifters. Solving unit 8 contains the first, second and third triggers.
    The device works as follows.
    Two rows of data T) and Dyp come from / two different channels and should be the same. The device investigates the mismatch of the two data rows D. and D,., The synchronization signal, having 14 the same nominal frequency as the synchronization signals H and Ihg of the mentioned series, but clearly defined phase, sets the operation of block 1, receiving signals D jp and , Block 1 compares the pre-synchronized signals H, DY and and supplies a representative Dry signal (divergence) of the data match test. To offset one signal relative to another (Fig. 2, the comparison times (signal C) correspond to the decay of the H-sync signal. At some moments (C signal) of this synchronization signal, there is a discrepancy between the two data signals D- and D) (p. Another mismatch signal a non-zero signal image (unequal bits b and bj in FIG. 3),
    Generator 3 is much lower than the rhythm of the numeric sequences and gives a signal of a rectangular shape h, defined; dividing packet of bits
    672
    the lengths (p / p is an integer) corresponding to the period of this signal h.
    The mismatch signal IY is laid in block 2 until the end of the packet defined by h, which is also superimposed on it. At the output of block 2, a PER (erroneous packet) j signal is signaled that the bit packet contains at least one mismatch between the data and Dy. Thus, this PER signal does not respond to a second error, which may exist in the same packet,
    In block 4, the PER signal is laid down in memory for the duration of the next packet, sending a signal h to the input of block 4.
    At the output of block 4 and ipylc, the NOCO mismatch is 1 for a given constant time if there is at least one mismatch of data in the previous packet. This constant pulse emitting time of NOCO must really be compatible with the work of the slower part of the device for correlating data. The described part, formed by blocks 1–4, operates at a frequency H and is a fast part, consciously reduced, due to energy consumption.
    The NOCO signal is fed to the input of counter 6, which counts NOCO pulses between two pulses offset by t from the INIT (initialization) signal supplied by counter 7. If counter 6 goes to its maximum count q, which is a given value before it arrives of another pulse of the INIT signal, it supplies them with a pulse of no correlation ABSCORR at the output (Fig. 4). If the pulse ABSCOORR is applied before the end of the time interval C, then counter 7 is initialized. In this case, and when counter 7 approaches tI11puls, the INIT initializes counter 6, Brem t, is selected to recognize the absence of correlation in sequences with the lowest transition content. In fact, the data transmitted usually via radio relay lines contain a raster of the actual data and a number of words or bits to systematically include. Thus, the frequency of the signal h, the trace, the packet length, is one of the parameters allowing to optimize the operation of the proposed correlator. 3 The packet length should take into account the content of the transitions of the considered data, as well as their temporal distribution. FIG. 3 depicts a special case when the length p of the packet is equal to the bits. The parameter q, which counts the NOCO pulses between two INIT pulses, is chosen so that the proposed correlator does not respond to errors that may exist on the data, and that pq is compatible with acceptable pulsation values. Such a correlator 10 is successfully used in the case of a request for switching beams to resolve the request T., ... for switching coming from a channel of order i, which means that channel i needs help or, if it already has it, that it does not wants more to have her. The signal is in 1 when channel i is in normal reception, and in O when channel i is assisted. Let's call the emergency channel. Then the series D-, connected to its synchronizer H | y, is compared with the series Dj, connected to its synchronizer Noug. The phase discriminator 11 receives synchronization signals and H, -pI outputs a representative phase displacement signal between synchronizers of two sequences. Thus, while the correlator 10, including elements 1,2, 4, 3 (Fig. 1), is experiencing data for discrepancies The discriminator 11 specifies the phase shift mode of the synchronizers at the input of the decision block 8. If 0 непри, there is an unacceptable phase shift, as it is too large, and the block 8 sends an ABSPHA signal, meaning no two phase sync synchronizers, at the input ementa OR 9, which in turn delivers the output pulse PAR (stepper), indicating poor phase. Block 8 also provides, when the phase is bad, a non-zero Signal N, which is fed to the input of Block 5, which also receives a T .. signal for switching channel i, and N O means that the signals are in phase. The signal N indicates the state in which the switch is: if N 1, channel i finds 674 s in normal transmission mode, if N O, the alarm channel X is active. When Tu ,, and N are in a different state, the block 5 sends a REC (search) signal allowing the search for the correct position of the emergency channel phase. The REC signal is fed to the input of counter 7 and is used to initialize it. The mismatch counter 6 counts the NOCO pulses between the two INIT pulses supplied by this counter 7 and if it approaches its maximum count q before the receipt of the INIT, it emits a no correlation pulse ABSCORR at the output, meaning that the data are in poor phase ratio. This ABSCORR signal, also applied to the input of the element OR 9, also allows the output of a PAP pulse. The ABSCORR signal turns on the counter 7. If there is no other ABSCORR pulse at the end of time t, then the counter 7 delivers a TTEST pulse to the input of block 8, which can depending on the state (p supplied by the discriminator 11, release the PAP pulse at the element output OR 9, imposing on it a representative impulse ABSPHA of a bad phase. Thus, the correlator 10 allows very quickly (it works in the rhythm of N.) phase coupling and, often, bad coupling between two digital rows, does not expect the discriminator 11, slower, will give its result. The selection of q pulses that allow PAP to be applied is such that it can be protected from possible errors as well as from rattling.The minimum test time for data in one position is the next Pn-c where iu is equal to the signal period H,. Conversely, a good result according to can still be confirmed by phase testing f at the end of time t-. The time intervals t testing follow one another and are selected by a duration compatible with the technology of correlator block 1O and discriminator 11. In decision block 8 there are three riggers that accept displacements The basics supplied by the discriminator 11 to their inputs D, as well as the TEST signal, coming from the output of counter 7. First of the triggers is included in 1 with the INIT signal supplied to. its input is Puset (pre-installation), the second of the flip-flops is included in the 0 signal of the PEG, arriving at its input Clear (resetting). The ABSPHA signal is present at the output O of the first of the flip-flops, while the output O of this flip-flop is connected to the clock input of the SC of the third of the flip-flops. This latter is set in the divider by 2 connection between its output O and
    its entrance is D.-.
    The switching request is received via the TR serial channel on the level of the node 12 for the channel formed by the data series D- +
    H and its corresponding sync signal. At the same time, the emergency channel x is received by block 13 and receives a phase
    H, in
    of these signals d
    dependencies
     BUT
    from the PAR signal in order to feed the input to the correlator. 10 and discriminator 1i, the numerical sequence D + Hjj.p, having the correct phase relationship with sequence i,
    requiring an emergency channel.
    D J)
    n
    HP
    H |
    Hi, HX
    CII I III I mm 11
    Fig g, n "b
    NOCO-1L P ajnLTLTUTJlJTJTJTJTJTJTJTJTJT n P P n, jf; INIT -,
    ABSCORRL
    If you want to
    权利要求:
    Claims (2)
    [1]
    1. NUMBER SEQUENCE PHASING DEVICE, comprising a first comparison unit, a pulse generator, a first memory unit, a counter, a phase shifter unit, characterized in that, in order to increase the reliability of the transmission, a second memory unit, an OR element, a second counter, and a second one are introduced into it comparison unit, deciding unit, phase discriminator, the output of the first comparison unit is connected to the first input of the first memory unit, the output of which is connected to the first input of the second memory unit, the output of the pulse generator is connected to the second inputs s first and second memory blocks, the second memory unit output is connected to a first input of the first counter, whose output is connected to first inputs of the OR gate and a second counter element output
    OR connected to the control input of the phase shifter unit, the first and second outputs of the second counter are connected respectively to the second input of the first counter and to the first input of the deciding unit, the first output of which is connected to the first input of the second comparison unit, the output of which is connected to the second input of the second counter, the second output the decision block is connected to the second input of the OR element, the output of the phase discriminator is connected to the second input of the decision block, the inputs of the first comparison unit, phase discriminator and information input The phase shifter blocks are the information inputs of the device, the input of the second comparison block is the control input of the device, the outputs of the phase shifter block are the information • outputs of the device, the first output of the resolving block is the control output of the device.
    [2]
    2. The device according to π. 1, characterized in that the decisive unit contains triggers, the output of the first trigger is connected to the first input of the second trigger, the second input of which is connected to its first output, the first inputs of the first and third triggers are combined and are the first input of the decisive block, the second inputs of the first and the third triggers are combined and are the second input of the decision block, the second output of the second trigger is the first output of the decision block, the output of the third trigger is the second output of the decision block.
    1 1181567
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    同族专利:
    公开号 | 公开日
    FR2505582B1|1985-06-07|
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    EP0064923B1|1986-04-09|
    EP0064923A1|1982-11-17|
    DE3270358D1|1986-05-15|
    FR2505582A1|1982-11-12|
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    IE53015B1|1988-05-11|
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    引用文献:
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    CA1059215A|1974-12-24|1979-07-24|Hideki Saito|Space diversity system in pcm-tdma telecommunication system using stationary communication satellite|
    US4119796A|1976-11-01|1978-10-10|Versitron, Inc.|Automatic data synchronizer|
    US4246656A|1978-10-24|1981-01-20|Raytheon Company|Diversity switch correlation system|
    FR2462066B1|1979-07-17|1988-01-15|Telecommunications Sa|DEVICE FOR SWITCHING TWO DIGITAL TRAINS|
    FR2462065A1|1979-07-24|1981-02-06|Thomson Csf|Switching of numeric signal equipment - using memory and coincidence detector techniques with two circuits transmitting same data under different conditions|
    ZA804386B|1979-08-10|1981-07-29|Plessey Co Ltd|Frame aligner for digital telecommunications exchange system|
    US4301537A|1979-11-06|1981-11-17|Bunker Ramo Corporation|Means and method for maintaining synchronization of a spread spectrum or other receiver clock|
    US4316285A|1980-09-11|1982-02-16|Bell Telephone Laboratories, Incorporated|Framing circuit for digital receiver|FR2574238B1|1984-12-04|1987-01-09|Telecommunications Sa|PHASE-OUT DEVICE FOR DIGITAL TRANSMISSION SYSTEMS|
    JPH047864B2|1986-05-23|1992-02-13|Fujitsu Ltd|
    FR2600474B1|1986-06-18|1988-08-26|Alcatel Thomson Faisceaux|METHOD FOR SYNCHRONIZING TWO BIN TRAINS|
    US5150386A|1987-05-19|1992-09-22|Crystal Semiconductor Corporation|Clock multiplier/jitter attenuator|
    US4805198A|1987-05-19|1989-02-14|Crystal Semiconductor Corporation|Clock multiplier/jitter attenuator|
    US4796280A|1987-11-06|1989-01-03|Standard Microsystems Corporation|Digital data separator|
    EP0618694A3|1993-04-01|1995-05-03|Ant Nachrichtentech|Method for synchronisation of travel time and clock phase of digital signals.|
    US6249557B1|1997-03-04|2001-06-19|Level One Communications, Inc.|Apparatus and method for performing timing recovery|
    US6756925B1|2003-04-18|2004-06-29|Northrop Grumman Corporation|PSK RSFQ output interface|
    DE102014212435A1|2014-06-27|2015-12-31|Robert Bosch Gmbh|Signal processing device for an autonomous service robot|
    法律状态:
    优先权:
    申请号 | 申请日 | 专利标题
    FR8109002A|FR2505582B1|1981-05-06|1981-05-06|DIGITAL TRAINS PHASING SYSTEM AND ITS APPLICATION TO SWITCHING SUCH TRAINS|
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